In semiconductor technologies, integrated circuit (IC) are formed in semiconductor substrates through various manufacturing steps, including lithography patterning, etching, deposition, ion implantation, and annealing. More particularly, the lithography patterning includes spin coating, baking exposure, post exposure baking, and developing. The etching includes dry etching and wet etching with different chemicals designed to effectively and selectively remove a certain material relative to a patterned mask layer. The deposition includes chemical vapor deposition, sputtering, atomic layer deposition, thermal oxidation, and plating. The ion implantation is designed to introduce impurities to a semiconductor substrate.
In semiconductor manufacturing, various processes, such as etching, deposition, implantation, and annealing, are performed in various processing tools, respectively. For example, a sputtering tool is designed to perform a sputtering deposition. Furthermore, a semiconductor manufacturer includes a plurality of processing tools of the same type designed to perform the same type process, such as sputtering deposition. It is expected that the plurality of processing tools match with each other such that the processing deviations among the processing tools are within a certain tolerable range.
Currently, there is no quantitative and systematic method for tool hardware match. The existing methods are not capable of exploring nonlinear relations among parameters and are even based on the intuitions. Especially, the tool match is more challenging when the semiconductor industry proceeds to advanced technology nodes. Accordingly, it would be desirable to provide a system and a method of tool match absent the disadvantages discussed above.